Study Guide 2016-2017

TIE-50206 Logic Synthesis, 5 cr

Implementation TIE-50206 2016-01

Lessons

Period 2 - 3
Methods of instruction Luento, Tentti, Harjoitukset
Person responsible Arto Perttula

Assessment scale

Numerical evaluation scale (0-5)

Requirements

Passed exam and accepted exercise work.

Exam Fri 03.03.2017 17:00 - 20:00
Exam Wed 19.04.2017 17:00 - 20:00
Exam Wed 11.10.2017 17:00 - 20:00
TIE-50206 Logic Synthesis/Lec/01 Mon 24.10.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 25.10.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Mon 31.10.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 01.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Mon 07.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 08.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 15.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 22.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 29.11.2016 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 10.01.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 17.01.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 24.01.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 31.01.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 07.02.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 14.02.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 Tue 21.02.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 24.10.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 26.10.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 26.10.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 31.10.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 02.11.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 02.11.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 07.11.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 09.11.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 09.11.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 14.11.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 16.11.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 16.11.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 21.11.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 23.11.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 23.11.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 28.11.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 30.11.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 05.12.2016 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 07.12.2016 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 07.12.2016 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 09.01.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 11.01.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 11.01.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 16.01.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 18.01.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 18.01.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 23.01.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 25.01.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 25.01.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 30.01.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 01.02.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 01.02.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 06.02.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 08.02.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 08.02.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 13.02.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 15.02.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 15.02.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 (*) Mon 20.02.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Wed 22.02.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 (*) Wed 22.02.2017 14:00 - 16:00

Study material

Type Name Author ISBN Additional information Language Examination material
Book RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Pong P. Chu 978-0471720928 Wiley-IEEE Press (April 14, 2006) English Yes
Lecture slides Logic synthesis slides Erno Salminen English Yes