TIE-12206 Post-graduate Seminar on Pervasive Computing, 1-8 cr

Implementation TIE-12206 2016-12

Description

In this seminar, you will study high-level synthesis (HLS), which is an emerging method to describe digital systems. In HLS, the system is described on a behavioral level using high-level languages such as C++. The main benefits of HLS are reduced development and verification time and fast architectural exploration. The course consists of seminar lectures where the participants take turns to present the lecture topics to each other, and exercises where simple applications are implemented in both VHDL and HLS to compare the two methods. Basic knowledge of digital design is required (e.g. TIE-50106 Digital Design) and experience in VHDL synthesis is recommended (e.g. TIE-50206 Logic Synthesis). After participating in this course, you will understand the principles of HLS and have some practical experience in using it to synthesize designs on FPGA. This seminar is worth 5 cr.

Lessons

Assessment scale

Evaluation scale passed/failed will be used on the course

Requirements

Participation in the seminar and accepted exercises

Study material