TIE-50406 DSP Implementations, 5 cr
Lisätiedot
Suitable for postgraduate studies.
Vastuuhenkilö
Jani Boutellier
Opetus
Toteutuskerta | Periodi | Vastuuhenkilö | Suoritusvaatimukset |
TIE-50406 2017-01 | 1 - 2 |
Jani Boutellier Sakari Lahti Saman Payvar |
option 1: Written exam and complete compulsory assignment, or option 2: Complete 75% of weekly exercises and completed compulsory assignments (will provide grade of 1-2) |
Osaamistavoitteet
Student can classify the special features of DSP processors and develop applications with fractional representation. Students can describe a DSP application with data flow graphs and analyze the inherent parallelism of the application. Students can realize a simple DSP algorithm on FPGA circuit.
Sisältö
Sisältö | Ydinsisältö | Täydentävä tietämys | Erityistietämys |
1. | number representations in fixed-point and floating-point processors | finite word length effects, overflow management | |
2. | DSP processor architectures | CISC, VLIW, SIMD | |
3. | memory architectures, Harvard architecture | parallel memories | |
4. | data-flow graph representation, loop and iteration bounds | folding of multirate systems | solving inequalities |
5. | pipelining, parallel processing, and combined parallel pipelined processing | low-power optimizations | |
6. | critical path, folding, unfolding, retiming | distributed arithmetic |
Ohjeita opiskelijalle osaamisen tasojen saavuttamiseksi
Written exam 70%, compulsory assignments 30%
Arvosteluasteikko:
Numerical evaluation scale (0-5)
Osasuoritukset:
Oppimateriaali
Tyyppi | Nimi | Tekijä | ISBN | URL | Lisätiedot | Tenttimateriaali |
Book | VLSI Digital Signal Processing Systems: Design and Implementation | K. K. Parhi | 0-471-24186-5 | No | ||
Lecture slides | Yes |
Tietoa esitietovaatimuksista
Basic knowledge on signal processing algorithms is recommended.
Vastaavuudet
Opintojakso | Vastaa opintojaksoa | Selite |
TIE-50406 DSP Implementations, 5 cr | TKT-3517 DSP Implementations, 5 cr | |
TIE-50406 DSP Implementations, 5 cr | TIE-50407 Data Processing Implementations, 5 cr |