Study Guide 2017-2018

TIE-50206 Logic Synthesis, 5 cr

Implementation TIE-50206 2017-01

Lessons

Period 2 - 3
Methods of instruction Luento, Tentti, Harjoitukset
Person responsible Joonas Multanen, Arto Perttula

Assessment scale

Numerical evaluation scale (0-5)

Requirements

Passed exam and accepted exercise work.

Exam Thu 01.03.2018 13:00 - 16:00
Exam Wed 25.04.2018 17:00 - 20:00
Exam Thu 25.10.2018 17:00 - 20:00
TIE-50206 Logic Synthesis/Lec/01 Tue 24.10.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Thu 26.10.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 31.10.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Thu 02.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 07.11.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Thu 09.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 14.11.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Thu 16.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 21.11.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 28.11.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 05.12.2017 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 09.01.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 16.01.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 23.01.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 30.01.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 06.02.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 13.02.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 20.02.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/01 Mon 23.10.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 24.10.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 25.10.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 30.10.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 31.10.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 01.11.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 06.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 07.11.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 08.11.2017 16:00 - 18:00
(Peruttu) TIE-50206 Logic Synthesis/E/01 Mon 13.11.2017 14:00 - 16:00
(Peruttu) TIE-50206 Logic Synthesis/E/02 Tue 14.11.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 15.11.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 20.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 21.11.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 22.11.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 27.11.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 28.11.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 29.11.2017 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 04.12.2017 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 05.12.2017 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Mon 08.01.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 09.01.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 10.01.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 15.01.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 16.01.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 17.01.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 22.01.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 23.01.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 24.01.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 29.01.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 30.01.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 31.01.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 05.02.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 06.02.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 07.02.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 12.02.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 13.02.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 14.02.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 19.02.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/02 Tue 20.02.2018 12:00 - 14:00
TIE-50206 Logic Synthesis/E/01 Wed 21.02.2018 16:00 - 18:00

Study material

Type Name Author ISBN Additional information Language Examination material
Book RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Pong P. Chu 978-0471720928 Wiley-IEEE Press (April 14, 2006) English Yes
Lecture slides Logic synthesis slides Arto Perttula English Yes