TIE-50406 DSP Implementations, 5 cr
Additional information
Suitable for postgraduate studies.
Person responsible
Jani Boutellier
Lessons
| Implementation | Period | Person responsible | Requirements |
| TIE-50406 2017-01 | 1 - 2 |
Jani Boutellier Sakari Lahti Saman Payvar |
option 1: Written exam and complete compulsory assignment, or option 2: Complete 75% of weekly exercises and completed compulsory assignments (will provide grade of 1-2) |
Learning Outcomes
Student can classify the special features of DSP processors and develop applications with fractional representation. Students can describe a DSP application with data flow graphs and analyze the inherent parallelism of the application. Students can realize a simple DSP algorithm on FPGA circuit.
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | number representations in fixed-point and floating-point processors | finite word length effects, overflow management | |
| 2. | DSP processor architectures | CISC, VLIW, SIMD | |
| 3. | memory architectures, Harvard architecture | parallel memories | |
| 4. | data-flow graph representation, loop and iteration bounds | folding of multirate systems | solving inequalities |
| 5. | pipelining, parallel processing, and combined parallel pipelined processing | low-power optimizations | |
| 6. | critical path, folding, unfolding, retiming | distributed arithmetic |
Instructions for students on how to achieve the learning outcomes
Written exam 70%, compulsory assignments 30%
Assessment scale:
Numerical evaluation scale (0-5)
Partial passing:
Study material
| Type | Name | Author | ISBN | URL | Additional information | Examination material |
| Book | VLSI Digital Signal Processing Systems: Design and Implementation | K. K. Parhi | 0-471-24186-5 | No | ||
| Lecture slides | Yes |
Additional information about prerequisites
Basic knowledge on signal processing algorithms is recommended.
Correspondence of content
| Course | Corresponds course | Description |
| TIE-50406 DSP Implementations, 5 cr | TKT-3517 DSP Implementations, 5 cr | |
| TIE-50406 DSP Implementations, 5 cr | TIE-50407 Data Processing Implementations, 5 cr |