TIE-51106 Computer Arithmetic , 5 cr
Computer Arithmetic
Additional information
Suitable for postgraduate studies.
Person responsible
Jarno Vanne, Timo D. Hämäläinen
Lessons
| Implementation | Period | Person responsible | Requirements |
| TIE-51106 2017-01 | 1 - 4 |
Jarno Vanne |
Exam. |
Learning Outcomes
Completing this course the students can perform addition, multiplication and division operations with different number systems and speeding-up techniques. In addition, they know implementation architectures at block diagram level and understand how accuracy and number of operands affect implementation architecture scalability.
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | Number systems and their basic properties. Conventional and Signed Digital numbers systems. Redundancy. Representation of complement numbers. | Non-conventional number systems. | |
| 2. | Addition and subtraction. Logical and technological speed-up methods. Addition of complement numbers. Adder implementations. | Parallel-prefix principile in fast addition. | |
| 3. | Multiplication. Mechanical and multiplier recoding for speed-up. Implementations. | ||
| 4. | Division. Restoring, non-restoring and SRT division speed-up methods. Implementations. | ||
| 5. | Floating point numbers, basic operations. Rounding and precision. Implementations. | Floating point standards and history. |
Instructions for students on how to achieve the learning outcomes
This course is passed by exam.
Assessment scale:
Numerical evaluation scale (0-5)
Study material
| Type | Name | Author | ISBN | URL | Additional information | Examination material |
| Book | Computer Arithmetic Algorithms | Koren | 1-56881-160-8 | No | ||
| Lecture slides | Computer Arithmetic Lecture Notes | Hämäläinen / Vanne | Available in POP | Yes |
Correspondence of content
| Course | Corresponds course | Description |
| TIE-51106 Computer Arithmetic , 5 cr | TIE-51100 Computer Arithmetic , 5 cr |