TIE-12206 Post-graduate Seminar on Pervasive Computing, 1-8 cr

Implementation TIE-12206 2017-13

Description

NOTE: we have increased the seats for this course and form three exercise groups to overcome space limitations in our PC class.


TUT, Nokia and Synopsys are organizing a special hands-on seminar course on modern digital ASIC design for master's and post-graduate students. The need for ASIC professionals is rapidly increasing in Finland, and passing this course opens excellent job and master's thesis opportunities in Nokia in spring 2018. This is also a great opportunity to learn from professionals in the field!

To attend this seminar course, you should already be familiar with FPGA and digital design flow. The course concentrates on the process of producing ASIC designs ready for fabrication from RTL designs. Preferred pre-requisite courses are TIE-50106 Digital design and TIE-50206 Logic Synthesis, or corresponding skills in digital design.

On the course, professional ASIC design tools from Synopsys are used together with modern technology libraries (32/90nm). A hands-on design case is worked on and processed throughout the course. The course covers all the essential stages and topics of a modern ASIC design:

RTL Synthesis to Netlist
Design-For-Test (DFT) and Automatic Test Pattern Generation (ATPG)
Floorplanning
Place and Route
Formal Equivalence Checking
Timing constraints and Static Timing Analysis (STA)
Chip Finishing (extraction, Design Rule Checking (DRC) and LVS)

The course consists of two 3-week intensive periods with lectures and exercises.

The timetable of the course is somewhat flexible, as this is an extra course.

This course is worth 8 credits.

Lessons

Assessment scale

Numerical evaluation scale (0-5)

Additional information of course implementation

Note! The lectures are recorded using Echo360 (video & audio). The recordings can be found in the Moodle2 area of the course.

Study material