TIE-50256 High-level Synthesis, 5 cr

Toteutuskerta TIE-50256 2018-01

Kuvaus

High-level synthesis (HLS) is the next step in raising the abstraction level of describing digital systems for FPGA/ASIC. Compared to VHDL/Verilog RTL, HLS allows a faster and more approachable design flow based on languages such as C/C++. On this course, you will learn the fundamentals of HLS and to implement real FPGA applications with it. This is a hands-on course with emphasis on practical exercises and project work.

Opetus

Arvosteluasteikko

Numerical evaluation scale (0-5)

Suoritusvaatimukset

Passed exam and exercises.

Kohderyhmät

Automaatiotekniikka , Automation Engineering/Machine Automation , DI- ja arkkitehtiopiskelijat , Electrical Engineering , Information Technology , International Students , Jatkotutkinto-opiskelijat , Science and Engineering, MSc (Tech) , Sähkötekniikka , Tietotekniikka

Oppimateriaali