TIE-51106 Computer Arithmetic , 5 cr
Lisätiedot
Suitable for postgraduate studies.
Vastuuhenkilö
Jarno Vanne, Timo D. Hämäläinen
Opetus
Toteutuskerta | Periodi | Vastuuhenkilö | Suoritusvaatimukset |
TIE-51106 2018-01 | 1 - 4 |
Jarno Vanne |
Exam. |
Osaamistavoitteet
Completing this course the students can perform addition, multiplication and division operations with different number systems and speeding-up techniques. In addition, they know implementation architectures at block diagram level and understand how accuracy and number of operands affect implementation architecture scalability.
Sisältö
Sisältö | Ydinsisältö | Täydentävä tietämys | Erityistietämys |
1. | Number systems and their basic properties. Conventional and Signed Digital numbers systems. Redundancy. Representation of complement numbers. | Non-conventional number systems. | |
2. | Addition and subtraction. Logical and technological speed-up methods. Addition of complement numbers. Adder implementations. | Parallel-prefix principile in fast addition. | |
3. | Multiplication. Mechanical and multiplier recoding for speed-up. Implementations. | ||
4. | Division. Restoring, non-restoring and SRT division speed-up methods. Implementations. | ||
5. | Floating point numbers, basic operations. Rounding and precision. Implementations. | Floating point standards and history. |
Ohjeita opiskelijalle osaamisen tasojen saavuttamiseksi
This course is passed by exam.
Arvosteluasteikko:
Numerical evaluation scale (0-5)
Oppimateriaali
Tyyppi | Nimi | Tekijä | ISBN | URL | Lisätiedot | Tenttimateriaali |
Book | Computer Arithmetic Algorithms | Koren | 1-56881-160-8 | No | ||
Lecture slides | Computer Arithmetic Lecture Notes | Hämäläinen / Vanne | Available in POP | Yes |
Vastaavuudet
Opintojakso | Vastaa opintojaksoa | Selite |
TIE-51106 Computer Arithmetic , 5 cr | TIE-51100 Computer Arithmetic , 5 cr |