Study Guide 2018-2019

TIE-50206 Logic Synthesis, 5 cr

Implementation TIE-50206 2018-01

Lessons

Period 2 - 3
Methods of instruction Luento, Tentti, Harjoitukset
Person responsible Onni Hytönen, Joonas Multanen, Arto Perttula

Assessment scale

Numerical evaluation scale (0-5)

Requirements

Passed exam and accepted exercise work.

Exam Thu 28.02.2019 13:00 - 16:00
Exam Tue 16.04.2019 17:00 - 20:00
Exam Tue 27.08.2019 17:00 - 20:00
TIE-50206 Logic Synthesis/Lec/01 Tue 23.10.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 26.10.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 30.10.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 02.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 06.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 09.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Tue 13.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 16.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 23.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 30.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 07.12.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 11.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 18.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 25.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 01.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 08.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 15.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 Fri 22.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/01 Mon 22.10.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 25.10.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 25.10.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 29.10.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 01.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 01.11.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 05.11.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 08.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 08.11.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Thu 15.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/01 Mon 19.11.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 22.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 22.11.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 26.11.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 29.11.2018 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 29.11.2018 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 03.12.2018 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Mon 07.01.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 10.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 10.01.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 14.01.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 17.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 17.01.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 21.01.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 24.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 24.01.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 28.01.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 31.01.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 31.01.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 04.02.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 07.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 07.02.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 11.02.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 14.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 14.02.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/E/01 Mon 18.02.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 Thu 21.02.2019 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Thu 21.02.2019 14:00 - 16:00

Study material

Type Name Author ISBN Additional information Language Examination material
Book RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Pong P. Chu 978-0471720928 Wiley-IEEE Press (April 14, 2006) English Yes
Lecture slides Logic synthesis slides Arto Perttula English Yes