TIE-50407 Data Processing Implementations, 5 cr
Additional information
Suitable for postgraduate studies.
Person responsible
Sakari Lahti, Jani Boutellier, Kai Jylkkä
Lessons
| Implementation | Period | Person responsible | Requirements |
| TIE-50407 2018-01 | 1 - 2 |
Jani Boutellier Kai Jylkkä Sakari Lahti |
Written exam and complete compulsory assignments |
Learning Outcomes
Student can classify the special features of data processing algorithms and develop applications with fractional representation. Students can describe a data processing application with a data flow graph and analyze the inherent parallelism of the application. Students can realize a simple data processing algorithm on an FPGA circuit and on a multicore processor.
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | number representations in fixed-point and floating-point processors | finite word length effects, overflow management | |
| 2. | Systolic architectures | ||
| 3. | CORDIC | ||
| 4. | data-flow graph representation, loop and iteration bounds | folding of multirate systems | solving inequalities |
| 5. | pipelining, parallel processing, and combined parallel pipelined processing | ||
| 6. | critical path, folding, unfolding, retiming |
Instructions for students on how to achieve the learning outcomes
Written exam 50%, compulsory assignments 50%
Assessment scale:
Numerical evaluation scale (0-5)
Partial passing:
Study material
| Type | Name | Author | ISBN | URL | Additional information | Examination material |
| Book | VLSI Digital Signal Processing Systems: Design and Implementation | K. K. Parhi | 0-471-24186-5 | No | ||
| Lecture slides | Yes |
Additional information about prerequisites
Basic knowledge on signal processing algorithms is recommended.
Programming skills, e.g. by the course "Programming 2" also mandatory
Correspondence of content
| Course | Corresponds course | Description |
| TIE-50407 Data Processing Implementations, 5 cr | TIE-50406 DSP Implementations, 5 cr |