Opinto-opas 2019-2020

TIE-50206 Logic Synthesis, 5 cr

Toteutuskerta TIE-50206 2019-01

Opetus

Periodi 2 - 3
Opetusmuodot Luento, Harjoitukset
Vastuuhenkilö Sakari Lahti, Joonas Multanen, Arto Perttula

Arvosteluasteikko

Numerical evaluation scale (0-5)

Suoritusvaatimukset

Passed exam and accepted exercise work.

Kohderyhmät

Information Technology , Tietotekniikka

TIE-50206 Logic Synthesis/Lec/01 Tue 22.10.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 24.10.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 29.10.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 31.10.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 05.11.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 07.11.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 Tue 12.11.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 14.11.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 21.11.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 28.11.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 05.12.2019 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 09.01.2020 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Thu 16.01.2020 14:00 - 16:00
TIE-50206 Logic Synthesis/Lec/01 (*) Tue 21.01.2020 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 (*) Tue 28.01.2020 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 (*) Tue 04.02.2020 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 (*) Tue 11.02.2020 10:00 - 12:00
TIE-50206 Logic Synthesis/Lec/01 (*) Tue 18.02.2020 10:00 - 12:00
TIE-50206 Logic Synthesis/E/02 Wed 23.10.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 23.10.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 24.10.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 30.10.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 30.10.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 31.10.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 06.11.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 06.11.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 07.11.2019 12:00 - 14:00
(Peruttu) TIE-50206 Logic Synthesis/E/01 Thu 14.11.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 20.11.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 20.11.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 21.11.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 27.11.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 27.11.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 28.11.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 04.12.2019 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 04.12.2019 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 05.12.2019 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 08.01.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 08.01.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 09.01.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 15.01.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 15.01.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 16.01.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 22.01.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 22.01.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 23.01.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 29.01.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 29.01.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 30.01.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 05.02.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 05.02.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 06.02.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 12.02.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 12.02.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 13.02.2020 12:00 - 14:00
TIE-50206 Logic Synthesis/E/02 Wed 19.02.2020 09:00 - 11:00
TIE-50206 Logic Synthesis/E/01 Wed 19.02.2020 16:00 - 18:00
TIE-50206 Logic Synthesis/E/01 (*) Thu 20.02.2020 12:00 - 14:00

Oppimateriaali

Tyyppi Nimi Tekijä ISBN Lisätiedot Kieli Tenttimateriaali
Book RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Pong P. Chu 978-0471720928 Wiley-IEEE Press (April 14, 2006) English Yes
Lecture slides Logic synthesis slides Arto Perttula English Yes