TIE-50256 High-level Synthesis, 5 cr
Lisätiedot
Suitable for postgraduate studies.
Vastuuhenkilö
Sakari Lahti, Jarno Vanne
Opetus
| Toteutuskerta | Periodi | Vastuuhenkilö | Suoritusvaatimukset |
| TIE-50256 2019-01 | 3 - 4 |
Sakari Lahti Jarno Vanne |
Passed exam and exercises. |
Osaamistavoitteet
After the course, the student can implement digital systems using C/C++ based high-level synthesis. The student understands the whole design flow from specification to implementation on FPGA. He/she can write the source code for the design, the test bench for it, and apply various optimizations with the high-level synthesis tool. The student will also understand the capabilities and limitations of high-level synthesis with respect to traditional RTL design flow.
Sisältö
| Sisältö | Ydinsisältö | Täydentävä tietämys | Erityistietämys |
| 1. | Fundamentals of high-level synthesis | General coding style, bit-accurate data types, pipelining, unrolling | |
| 2. | Scheduling of IO and memories | Unconditional/conditional IO | |
| 3. | Sequential and combinational hardware | Shift registers, multiplexors, shifters, accumulators, adder trees, lookup tables | |
| 4. | Memory architecture | Memory organization, caching | |
| 5. | Hierarchical design | Sharing arrays, sharing control variables, reconvergence, channels, arbitration, feedback | |
| 6. | Example designs | FIR filter, FFT |
Oppimateriaali
| Tyyppi | Nimi | Tekijä | ISBN | URL | Lisätiedot | Tenttimateriaali |
| Book | High-Level Synthesis Blue Book | Michael Fingeroff | 978-1450097246 | The book is available in electric format to the students | No | |
| Lecture slides | No |
Esitietovaatimukset
| Opintojakso | P/S | Selite |
| TIE-02201 Ohjelmointi 2: Perusteet | Mandatory | 1 |
| TIE-02207 Programming 2: Basics | Mandatory | 1 |
| TIE-50100 Digitaalisuunnittelu | Mandatory | 2 |
| TIE-50106 Digital Design | Mandatory | 2 |
| TIE-50206 Logic Synthesis | Advisable |
1 . C programming
2 . Digital design
Tietoa esitietovaatimuksista
The student should know the basics of digital design and C/C++ programming before attending this course. Knowledge of VHDL/Verilog HDL is also useful, but not mandatory.
Vastaavuudet
Opintojakso ei vastaan mitään toista opintojaksoa