TKT-1560 DIGITAALISUUNNITTELU III, 5 cr
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Person responsible
Jarmo Takala
Lecturers
Jarmo Takala, Professor, TG408
Lecture room and time
Per II: Monday 12 - 16, TB224
Implementation rounds
Implementation 1
Period 1 | Period 2 | Period 3 | Period 4 | Period 5 | Summer | Language of instruction | |
Lecture | - | 4 h/week | - | - | - | - | In English only |
Exercise | - | 2 h/week+ | 2 h/week | - | - | - | In Finnish and English |
Assignment | - | - | 24 h/per | - | - | - | In Finnish and English |
Exam | In English only |
Objectives
After passing the course, the students are able to design applications-specific hardware structures containing parallelism and optimize the structures for low power consumption.
Contents
Content | Core content | Complementary knowledge | Specialist knowledge |
1. | Data-flow graph representations and loop and iteration bounds | Register minimization techniques | Algorithmic and numerical strength reduction |
2. | Pipelining, parallel processing, and combined pipelining and parallel processing | Low-power optimizations | Redundant arithmetic |
3. | Critical path, folding, unfolding, and retiming | Distributed arithmetic | |
4. | Systolic arrays |   |
Requirements for completing the course
written exam and completed compulsory assignment
Assessment criteria
Written exam 70%, compulsory assignment 30%
Study material
Type | Name | Author | ISBN | URL, edition, availablitity... | Exam material | Language |
Book | VLSI Digital Signal Processing Systems: Design and Implementation | K. K. Parhi | 0-471-24186-5 | No | ||
Lecture slides | No |
Prerequisites
Number | Name | Credits | M/R |
SGN-2010 | Digital Linear Filtering I | 5 | Recommendable |
TKT-1210 | Digital Design II | 5 | Mandatory |
TKT-1400 | ASIC Design I | 5 | Recommendable |
Other comments
Last modified | 30.01.2005 |
Modified by | Jarmo Takala |