Courses persons responsible
Claudio Brunelli

Lecturers
Claudio Brunelli

Implementations

	Period 1	Period 2	Period 3	Period 4	Period 5	Summer
Lecture	-	-	-	2 h/week	2 h/week	-
Exercise	-	-	-	1 h/week	1 h/week	-
Exam

(Timetable for academic year 2007-2008)

Objectives
The student learns how to to design and implement simple digital cicuits using hardware description languages, and gets familiar with the related simulation and synthesis software tools.

Content

Content	Core content	Complementary knowledge	Specialist knowledge
1.	Syntax and properties of VHDL and Verilog hardware description languages.	Design flows: from VHDL model to ASIC/FPGA implementation.
2.	General-purpose and application specific hardware description languages.
3.	Module generators and parametrized hardware descriptions.
4.	Reusability when using hardware description languages.
5.	Logic synthesis

Evaluation criteria for the course

Study material

Type	Name	Auhor	ISBN	URL	Edition, availability...	Exam material	Language
Book	VHDL Made Easy!	D. Pellerin, D. Taylor	0-13-650763-8		Prentice Hall, 1997.	Yes	English

Prerequisites
Prequisite relations (Sign up to TUT Intranet required)

Additional information about prerequisites
Basic understanding of how to design simple state machines and hierarchical systems are needed as previous knowledge for this course.

Distance learning

- In information distribution via homepage, newsgroups or mailing lists, e.g. current issues, timetables
- In distributing and/or returning exercise work, material etc

- Contact teaching: 80 %
- Distance learning: 0 %
- Proportion of a student's independent study: 20 %

Scaling

Methods of instruction	Hours
Lectures	24
Exercises	68

Study materials	Hours
study material	21

Other scaled	Hours
	10
Total sum	123

Correspondence of content
8404129 Hardware Description Languages

Course homepage

Last modified	08.02.2007
Modified by	Olli Vainio