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Course Catalog 2010-2011
TKT-1506 ASIC Design II, 5 cr |
Person responsible
Olli Vainio
Requirements
Exam and compulsory exercise work.
Completion parts must belong to the same implementation
Principles and baselines related to teaching and learning
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Learning outcomes
After completing the course the student can - Explain the ASIC design flow - Describe main trends of technology evolution - Identify parasitic elements in integrated circuits and analyze their effect on circuit performance - Describe methods and algorithms for floorplanning, placement and routing - Explain how system chips are composed of reused cores
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | Transistors, wires, and parasitic components in ICs. | ||
| 2. | Floorplanning, clock tree generation, supply wiring, and the nonidealities therein. | ||
| 3. | Placement and routing of standard cells, netlist extraction, backannotation. | ||
| 4. | Cell design and optimization, timing issues, memory cell design. | ||
| 5. | Large system chips. |
Study material
| Type | Name | Author | ISBN | URL | Edition, availability, ... | Examination material | Language |
| Book | Digital Integrated Circuits: A Design Perspective | J.M. Rabaey, A. Chandrakasan, B. Nicolic | 0-13-120764-4 | 2nd edition | English | ||
| Online book | Application-Specific Integrated Circuits | M. J. S. Smith | 0-201-50022-1 | http://www.edacafe.com/books/ASIC/ASICs.php | English |
Prerequisite relations (Requires logging in to POP)
Correspondence of content
There is no equivalence with any other courses
Additional information
The course is given only every other year.
Suitable for postgraduate studies