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Course Catalog 2011-2012
TKT-3416 Computer Architecture, 7 cr |
Additional information
The course is intended for international students, primarily in the Information Technology degree programme. The course is mutually exclusive with TKT-3200 Tietokonetekniikka I (TKT-3206 Computer Architecture I) and TKT-3400 Tietokonetekniikka II (TKT-3406 Computer Architecture II) because of overlapping contents.
Person responsible
Fabio Garzia
Lessons
| Study type | P1 | P2 | P3 | P4 | Summer | Implementations | Lecture times and places |
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Requirements
Accepted exercise projects, one pen and paper exercise, and final exam.
Learning outcomes
The student learns to - identify the structure and the basic components of a computer architecture; - compare different architectures in terms of performance; - classify and compare the mechanisms that allow to increase the performance of a computer architecture; - reproduce the behavior of different kinds of architectures and functional blocks; - suggest how to improve the performance in a given architecture
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | Instruction Set Architecture. Classification of ISA. | Instruction format, operands, addressing modes in a load/store architecture(MIPS). | ISA of a memory/register architecture (IA32). |
| 2. | Assessing the performance of a computer architecture. Ahmdal's Law. Architecture of a single-cycle machine. | Architecture of a multi-cycle machine. Micro-code and micro-instruction implementation. | |
| 3. | Arithmetic, control and memory subsystem implementation principles. Pipelining, memory hierarchy, cache memories. | Floating-point arithmetic, forwarding in pipelines, addressing modes, virtual memory, interrupt handling. | GPUs and multimedia support in instruction sets. |
| 4. | Dynamic use of parallelism. Tomasulo algorithm, branch prediction, conditional execution. Instruction-level parallelism and its limitations. | Superscalar processors, speculative execution. Utilization of parallelism in software. | IA-32 and X86-64 ISAs |
| 5. | VLIW, TTA and EPIC architectures and their compiler support. Static and compiler-assisted parallelism. | Parallelism in embedded systems. | IA-64 ISA |
| 6. | Enhancing cache memory performance. Parallel memory architectures. | Memory hierarchy design. | |
| 7. | Multiprocessor architectures and thread-level parallelism. Communication and synchronization between processors and processes. Interconnections and clustering. | Performance analysis of I/O systems. Multiprocessor systems cache coherence. |
Evaluation criteria for the course
The grade is granted according to the exam results and the bonus points collected in the execution of the pen&paper exercises and exercise projects. The exam is characterized by a maximum of 38 points. The course is passed if and only if the student collects at least 15 points at the exam, gets one point from the P&P exercises and complete all the exercise projects.
Assessment scale:
Numerical evaluation scale (1-5) will be used on the course
Study material
| Type | Name | Author | ISBN | URL | Edition, availability, ... | Examination material | Language |
| Book | Computer Architecture: a Quantitative Approach | Hennessy and Patterson | 978-0123704900 | English | |||
| Book | Computer Organization and Design: The Hardware/Software Interface | Hennessy and Patterson | 978-1558604285 | English |
Prerequisite relations (Requires logging in to POP)
Correspondence of content
There is no equivalence with any other courses
More precise information per implementation
| Implementation | Description | Methods of instruction | Implementation |
| Lectures Excercises Practical works |
Contact teaching: 0 % Distance learning: 0 % Self-directed learning: 0 % |