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Course Catalog 2012-2013
TLT-8307 RF-ASIC Design - 1, 7 cr |
Person responsible
Jani Järvenhaara, Nikolay. T Tchamov, Juho Ylönen
Lessons
| Study type | P1 | P2 | P3 | P4 | Summer | Implementations | Lecture times and places |
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Requirements
1. Exam.
2. Attending at least 80% of the Lectures.
3. Attending all Exercises.
4. Developing all Homeworks.
5. Completing all Laboratory Exercises.
Completion parts must belong to the same implementation
Principles and baselines related to teaching and learning
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Learning outcomes
Major practical course for BSc and MSc levels targeting the Methods and Skills of the design of a modern Monolithic RF Integrated Circuits and to serve as Graduation Work for BSc Students. This course is designed to meet the most recent demands of the Industry for Practical Designer Knowledge & Skills in the three years of B.Sc. curricula and as well for those who continue toward the MSc level. The student is able to: - Evaluate silicon active and passive components in the GHz range like Transistors, Inductors, Varactors, Capacitors, Contact/Bonding Pads etc. - Perform simulations, layout design and parasitic extraction on an existing electrical design. Target circuit for design is currently a GHz-range Clapp LC Oscillator architecture on 90nm CMOS Generic PDK of Cadence. - Perform VCO measurements using spectrum analyzer and VCO/PLL measurement system.
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | The RF-ASIC Design Flow and Cadence Tools on 90 nm GPDK. CMOS Semiconductor Processes, characterization and layout of integrated CMOS and Bipolar Transistors, Capacitors and Inductors. | ||
| 2. | Course Circuit Design Task Introduction: A 1-2 GHz Clapp Oscillator and its components in the monolithic integration on Silicon. Additional blocks to the oscillator design task: Current Mirror and Buffer. Oscillator Phase Noise Simulation. | ||
| 3. | Design for Manufacturing. Design Extracted RF-Parasitics evaluation and Compensation. Preparing the final Database and GDSII file. Design Documentation and Presentation. | ||
| 4. | IC Measurement set-up and its Modeling in Cadence. R&S FSEM Spectrum Analyzer and HP 4352B VCO/PLL Measurement System. Automated VCO Measurements under HP-VEE control. |
Evaluation criteria for the course
Exam.
Assessment scale:
Numerical evaluation scale (1-5) will be used on the course
Partial passing:
Study material
| Type | Name | Author | ISBN | URL | Edition, availability, ... | Examination material | Language |
| Other literature | CADENCE and semiconductor process manuals | English |
Prerequisites
| Course | Mandatory/Advisable | Description |
| TLT-8207 Communication Circuits & Modules - 1 | Advisable |
Additional information about prerequisites
Note: In case you have taken other course(s) which you might consider to be compatible with the Pre-requisite one above, please contact the Course Coordinator for approval.
Prerequisite relations (Requires logging in to POP)
Correspondence of content
| Course | Corresponds course | Description |
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More precise information per implementation
| Implementation | Description | Methods of instruction | Implementation |