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Course unit, curriculum year 2021–2022
COMP.CE.420
System-on-Chip Verification, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 3 (1.1.2022–6.3.2022)
Active in period 4 (7.3.2022–15.5.2022)
Course code
COMP.CE.420Language of instruction
EnglishAcademic years
2021–2022, 2022–2023, 2023–2024Level of study
Advanced studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Arto OinonenResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
- Fundamental concepts in SoC verification
- Object-oriented properties of SystemVerilog language
- Universal Verification Methodology (UVM)
Complementary knowledge
- UVM on integration level
- Formal verification
- SystemVerilog as design language
Specialist knowledge
- UVM Register Abstraction Layer
- SystemVerilog DPI
Learning outcomes
Prerequisites
Recommended prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Grade 1 is given for students who complete the exercises with a defined number of points. Grades 2-5 can be achieved by taking the voluntary exam.
Participation in teaching
10.01.2022 – 29.04.2022
Active in period 3 (1.1.2022–6.3.2022)
Active in period 4 (7.3.2022–15.5.2022)
02.05.2022 – 13.05.2022
Active in period 4 (7.3.2022–15.5.2022)