Course unit, curriculum year 2024–2025
COMP.CE.420
System-on-Chip Verification, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 3 (1.1.2025–2.3.2025)
Active in period 4 (3.3.2025–31.5.2025)
Course code
COMP.CE.420Language of instruction
EnglishAcademic years
2024–2025, 2025–2026, 2026–2027Level of study
Advanced studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Arto OinonenResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
- Fundamental concepts in SoC verification
- Object-oriented properties of SystemVerilog language
- Universal Verification Methodology (UVM)
Complementary knowledge
- UVM on integration level
- Formal verification
Specialist knowledge
- UVM Register Abstraction Layer
- SystemVerilog DPI
Learning outcomes
Prerequisites
Recommended prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Grade 1 is given for students who complete the exercises with a defined number of points. Grades 2-5 can be achieved by taking the voluntary exam.
Completion of all options is required.
Exam
No scheduled teaching
Participation in teaching
07.01.2025 – 30.05.2025
Active in period 3 (1.1.2025–2.3.2025)
Active in period 4 (3.3.2025–31.5.2025)