Digital Design, 5 cr

Tampere University

Teaching periods

Course code

COMP.CE.200

Language of instruction

English, Finnish

Academic years

2024–2025, 2025–2026, 2026–2027

Level of study

Intermediate studies

Grading scale

General scale, 0-5

Persons responsible

Responsible teacher:

Sakari Lahti

Responsible organisation

Faculty of Information Technology and Communication Sciences 100 %

Coordinating organisation

Computing Sciences Studies 100 %

Specification, design and analysis of synchronous logic. Different levels of description abstractions in digital systems.
Combinational gate networks. Two and multi-level gate networks. Critical path and maximum clock frequency.
Sequential networks. Mealy and Moore state machines. Timing analysis and determination of clock speed.
Standard modules. Connecting modules using bus structures. Data and control paths. Register Transfer Level.
FPGA architecture and usage in digital design. Design tools and methodologies.

The Y-model: behaviour, architecture and mapping. Hierarchical design.
Propagation delay. Fan-in and fan-out. Loading of the gates.
Extended state machines with memory. Registered state machine.
Two's complement representation. Binary addition, subtraction, and multiplication.
FPGA boards with peripherals. Practical designs.
Understanding data sheets.

Learning outcomes

Recommended prerequisites

Further information

Learning material

Equivalences

Kokonaisuudet, joihin opintojakso kuuluu

Completion option 1

Passing the compulsory exercises and exam.

Completion of all options is required.