Course unit, curriculum year 2024–2025
COMP.CE.320
High-level Synthesis, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 1 (1.8.2024–20.10.2024)
Active in period 2 (21.10.2024–31.12.2024)
Active in period 3 (1.1.2025–2.3.2025)
Course code
COMP.CE.320Language of instruction
EnglishAcademic years
2024–2025, 2025–2026, 2026–2027Level of study
Advanced studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Sakari LahtiResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
- Fundamentals of high-level synthesis
- Scheduling of IO and memories
- Sequential and combinational hardware
- Memory architecture
- Hierarchical design
Complementary knowledge
- General coding style, bit-accurate data types, pipelining, unrolling
- Unconditional/conditional IO
- Shift registers, multiplexers, shifters, accumulators, adder trees, lookup tables
- Memory organization, caching
- Sharing arrays, sharing control variables, reconvergence, channels, arbitration, feedback
- FIR filter, FFT examples
Learning outcomes
Prerequisites
Compulsory prerequisites
Recommended prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Passed exam and exercises.
Completion of all options is required.
Participation in teaching
26.08.2024 – 08.12.2024
Active in period 1 (1.8.2024–20.10.2024)
Active in period 2 (21.10.2024–31.12.2024)
Exam
09.12.2024 – 29.12.2024
Active in period 2 (21.10.2024–31.12.2024)
30.12.2024 – 19.01.2025
Active in period 2 (21.10.2024–31.12.2024)
Active in period 3 (1.1.2025–2.3.2025)
20.01.2025 – 09.02.2025
Active in period 3 (1.1.2025–2.3.2025)