Opinto-opas 2008-2009 Perus Perus Pori KV Jatko Avoin |Tutkinnot|     |Opintokokonaisuudet|     |Opintojaksot|

Opintojakson vastuuhenkilö

Jani Järvenhaara, Sami Sipilä, Nikolay Tchamov

Toteutuskerrat

	Luentoajat ja -paikat	Kohderyhmä, jolle suositellaan
Toteutus 1	Per 4 : Torstai 9 - 11, TC173

Suoritusvaatimukset

1. Exam. 2. Attending at least 80% of the Lectures. 3. Attending all Exercises. 4. Developing all Homeworks. 5. Completing all Laboratory Exercises.
Osasuoritusten pitää liittyä samaan toteutuskertaan

Opetukseen ja oppimiseen liittyvät periaatteet ja lähtökohdat

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Tavoitteet

Major practical course for BSc and MSc levels targeting the Methods and Skills of the design of a modern Monolithic RF Integrated Circuits and to serve as Graduation Work for BSc Students. This course is designed to meet the most recent demands of the Industry for Practical Designer Knowledge & Skills in the three years of B.Sc. curricula and as well for those who continue toward the MSc level. It serves as complete course for preparing the BSc engineer to design the implementation, the fabrication and the measurement on modern BiCMOS and CMOS Si-process using the integrated tools of CADENCE and modern GHz-range Spectrum Analyzer and VCO/PLL Measurement System. The course is introducing and then developing the Designer's Tool Box of Set-ups for Evaluation of all Silicon Active and Passive Components in the GHz range like Transistors, Inductors, Varactors, Capacitors, Contact/Bonding Pads etc. From the circuit idea, via electric design simulations, layout floor plan, components design and extracted parasitics simulations, and concluding with the GDSII database development and debugging. Target circuit for design is currently a GHz-range Clapp LC Oscillator architecture on 90nm CMOS Generic PDK of Cadence.

Sisältö

Sisältöalue	Ydinaines	Täydentävä tietämys	Erityistietämys
1.	The RF-ASIC Design Flow and Cadence Tools. CMOS Semiconductor Processes, characterization and layout of integrated CMOS and Bipolar Transistors,Capacitors and Inductors.
2.	Course Circuit Design Task Introduction: The Clapp Oscillator and its components in the monolithic integration on Silicon. Additional blocks to the oscillator design task: Current Mirror and Buffer. Oscillator Phase Noise Simulation.
3.	Design for Manufacturing. Design Extracted RF-Parasitics evaluation and Compensation. Preparing the final Database and GDSII file. Design Documentation and Presentation.
4.	IC Measurement set-up and its Modeling in Cadence. Spectrum Analyzer and VCO/PLL Measurement System. Automated VCO Measurements under HP-VEE control.

Opintojakson arvostelu

Exam.

Arvosteluasteikko:

Opintojaksolla käytetään numeerista arviointiasteikkoa (1-5)

Osasuoritukset:

Osasuoritusten pitää liittyä samaan toteutuskertaan

Oppimateriaali

Tyyppi	Nimi	Tekijä	ISBN	URL	Painos,saatavuus...	Tenttimateriaali	Kieli
Muu kirjallisuus	CADENCE and semiconductor process manuals						Englanti

Esitietovaatimukset

Vastaavuudet

Tarkempia tietoja toteutuskerroittain

	Kuvaus	Opetusmuodot	Toteutustapa
Toteutus 1		Luennot Harjoitukset Laboratoriotyöt	Lähiopetus: 0 % Etäopetus: 0 % Itseopiskelu: 0 %

Viimeksi muokattu	20.01.2009
Muokkaaja	Sami Sipilä