Course Catalog 2009-2010 International Basic Pori International Postgraduate Open University |Degrees|     |Study blocks|     |Courses|

Person responsible

Jani Järvenhaara, Nikolay Tchamov

Implementations

	Lecture times and places	Target group recommended to
Implementation 1	Per 4 : Thursday 9 - 11, TC173

Requirements

1. Exam. 2. Attending at least 80% of the Lectures. 3. Attending all Exercises. 4. Developing all Homeworks. 5. Completing all Laboratory Exercises.
Completion parts must belong to the same implementation

Principles and baselines related to teaching and learning

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Learning outcomes

Major practical course for BSc and MSc levels targeting the Methods and Skills of the design of a modern Monolithic RF Integrated Circuits and to serve as Graduation Work for BSc Students. This course is designed to meet the most recent demands of the Industry for Practical Designer Knowledge & Skills in the three years of B.Sc. curricula and as well for those who continue toward the MSc level. It serves as complete course for preparing the BSc engineer to design the implementation, the fabrication and the measurement on modern BiCMOS and CMOS Si-process using the integrated tools of CADENCE and modern GHz-range Spectrum Analyzer and VCO/PLL Measurement System. The course is introducing and then developing the Designer's Tool Box of Set-ups for Evaluation of all Silicon Active and Passive Components in the GHz range like Transistors, Inductors, Varactors, Capacitors, Contact/Bonding Pads etc. From the circuit idea, via electric design simulations, layout floor plan, components design and extracted parasitics simulations, and concluding with the GDSII database development and debugging. Target circuit for design is currently a GHz-range Clapp LC Oscillator architecture on 90nm CMOS Generic PDK of Cadence.

Content

Content	Core content	Complementary knowledge	Specialist knowledge
1.	The RF-ASIC Design Flow and Cadence Tools. CMOS Semiconductor Processes, characterization and layout of integrated CMOS and Bipolar Transistors,Capacitors and Inductors.
2.	Course Circuit Design Task Introduction: The Clapp Oscillator and its components in the monolithic integration on Silicon. Additional blocks to the oscillator design task: Current Mirror and Buffer. Oscillator Phase Noise Simulation.
3.	Design for Manufacturing. Design Extracted RF-Parasitics evaluation and Compensation. Preparing the final Database and GDSII file. Design Documentation and Presentation.
4.	IC Measurement set-up and its Modeling in Cadence. Spectrum Analyzer and VCO/PLL Measurement System. Automated VCO Measurements under HP-VEE control.

Evaluation criteria for the course

Exam.

Assessment scale:

Numerical evaluation scale (1-5) will be used on the course

Partial passing:

Completion parts must belong to the same implementation

Study material

Type	Name	Author	ISBN	URL	Edition, availability, ...	Examination material	Language
Other literature	CADENCE and semiconductor process manuals						English

Prerequisites

Additional information about prerequisites
Note: In case you have taken other course(s) which you might consider to be compatible with the Pre-requisite one above, please contact the Course Coordinator for approval.

Correspondence of content

More precise information per implementation

	Description	Methods of instruction	Implementation
Implementation 1		Lectures Excercises Laboratory assignments	Contact teaching: 0 % Distance learning: 0 % Self-directed learning: 0 %

Last modified	16.11.2009
Modifier	Virpi Hämäläinen