TIE-50406 DSP Implementations, 5 cr

Additional information

Suitable for postgraduate studies

Person responsible

Jarmo Takala

Lessons

Implementation 1: TIE-50406 2015-01

Study type P1 P2 P3 P4 Summer

Lectures
Excercises
Assignment
4 h/week
2 h/week

+2 h/week
20 h/per

Lecture times and places: Monday 14 - 16 TB224 , Tuesday 12 - 14 TB223

Requirements

option 1: Written exam and complete compulsory assignment, or option 2: Complete 75% of weekly exercises and completed compulsory assignments (will provide grade of 1-2)
Completion parts must belong to the same implementation

Learning Outcomes

Student can classify the special features of DSP processors and develop applications with fractional representation. Students can describe a DSP application with data flow graphs and analyze the inherent parallelism of the application.

Content

Content Core content Complementary knowledge Specialist knowledge

1. number representations in fixed-point and floating-point processors finite word length effects, overflow management

2. DSP processor architectures CISC, VLIW, SIMD

3. memory architectures, Harvard architecture parallel memories

4. data-flow graph representation, loop and iteration bounds folding of multirate systems solving inequalities

5. pipelining, parallel processing, and combined parallel pipelined processing low-power optimizations

6. critical path, folding, unfolding, retiming distributed arithmetic

7. general-purpose graphics processing units OpenCL

Instructions for students on how to achieve the learning outcomes

Written exam 70%, compulsory assignments 30%

Assessment scale:

Numerical evaluation scale (1-5) will be used on the course

Partial passing:

Completion parts must belong to the same implementation

Study material

Type Name Author ISBN URL Additional information Examination material

Book VLSI Digital Signal Processing Systems: Design and Implementation K. K. Parhi 0-471-24186-5 No

Lecture slides Yes

Additional information about prerequisites
Basic knowledge on signal processing algorithms is recommended.

Correspondence of content

Course Corresponds course Description

TIE-50406 DSP Implementations, 5 cr TKT-3517 DSP Implementations, 5 cr

Last modified 26.02.2015

Study type	P1	P2	P3	P4	Summer
Lectures Excercises Assignment	4 h/week 2 h/week	+2 h/week 20 h/per

Content	Core content	Complementary knowledge	Specialist knowledge
1.	number representations in fixed-point and floating-point processors	finite word length effects, overflow management
2.	DSP processor architectures	CISC, VLIW, SIMD
3.	memory architectures, Harvard architecture	parallel memories
4.	data-flow graph representation, loop and iteration bounds	folding of multirate systems	solving inequalities
5.	pipelining, parallel processing, and combined parallel pipelined processing	low-power optimizations
6.	critical path, folding, unfolding, retiming	distributed arithmetic
7.	general-purpose graphics processing units	OpenCL

Type	Name	Author	ISBN	URL	Additional information	Examination material
Book	VLSI Digital Signal Processing Systems: Design and Implementation	K. K. Parhi	0-471-24186-5			No
Lecture slides						Yes

Course	Corresponds course	Description
TIE-50406 DSP Implementations, 5 cr	TKT-3517 DSP Implementations, 5 cr