I am currently working as an Assistant Professor (Tenure Track), Computer Engineering at the Faculty of Information Technology and Communication Sciences, Tampere University, Finland. Previously, I was working as a Research Assistant Professor (RAP) at the ECE department of the Hong Kong University of Science and Technology (HKUST). 

From Oct. 2019 - Oct. 2022, I was a postdoctoral researcher at the Integrated Systems for Information Processing (ISIP) Lab at McGill University, Canada. At McGill, I was working with Prof. Warren J. Gross. I received my Ph.D. in 2017, from the Department of Electronics and Computer Engineering (ECE) at HKUST under Prof. Chi-Ying Tsui's supervision.

My research focuses on development of high-throughput, low-latency and energy-efficient VLSI architectures for baseband processing systems, specifically channel code decoders. In addition, my curiosity is fueled by topics such as information theory, VLSI Design, Massive MIMO, 5G/6G, Compute-In-Memory (CiM), URLLC, Green Communication and Universal Channel Code decoders. 

• VLSI Design (ASIC/FPGA)
• SoC Design
• Information theory 
• Channel Coding 
• Wireless Communications (5G/6G)
• Massive MIMO
• Compute-In-Memory (CiM)

Research Assistant Professor (RAP)  (ECE Department)

 November 2023 – August 2024

Hong Kong University of Science and Technology (HKUST), Hong Kong   

Postdoctoral Fellow (Division of Integrative Systems and Design)

 November 2022 – November 2023

Hong Kong University of Science and Technology (HKUST), Hong Kong   

Post Doctoral Researcher (Integrated Systems for Information Processing (ISIP) Lab)

October  2019 - 30th September  2022

McGill University, Canada                        

Lead Engineer (Hong Kong Applied Science and Technology Research Institute  (ASTRI) 

September  2017 - September  2019

Baseband Solutions, Communication Technology Division                        

Teaching Experience  (TA, HKUST)

• ELEC 2200 - Digital Circuits and Systems (2013-2016)
• EESM 5020 - Digital VLSI System Design and Design Automation (2016)
• EESM 5060 - Embedded Systems (2012,2016-2017)
• ELEC 4410 - CMOS VLSI Design (2013)

Education:

Electronics and Computer Engineering, Doctor of Philosophy (PhD)

• August 2012 – August 2017 (PhD. Advisor: Prof. Chi-Ying Tsui)
• Hong Kong University of Science and Technology (HKUST), Hong Kong
• Ph.D. Thesis: Design of low complexity and high throughput baseband processing blocks for 5G wireless communication

Computer Science and Engineering, Master of Science (MSc)

• August 2009 – August 2011 (Msc. Advisor: Prof. Sangju Park)
• Hanyang University, South Korea

Computer Engineering, Bachelor of Science (BSc)

• September 2003 – September 2007
• University of Engineering and Technology Taxila, Pakistan

Book 

• S. M. Abbas, Marwan Jalaleddine and Warren J. Gross, “Guessing Random Additive Noise Decoding: A Hardware Perspective”  ISBN 3031316622, 9783031316623, Springer Nature Switzerland, 2023.

Book Chapters

• S. M. Abbas and Chi-Ying Tsui, “Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO” System-on-Chip in the Nanoscale Era – Design, Verification and Reliability. VLSI-SoC 2016. IFIP Advances in Information and Communication Technology, vol 508. Springer, Cham. https://doi.org/10.1007/978-3-319-67104-8_10.

Journal Papers

• S. M. Abbas, Marwan Jalaleddine and Warren J. Gross, “List-GRAND: A practical way to achieve Maximum Likelihood Decoding", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 1, pp. 43-54, Jan. 2023, doi: 10.1109/TVLSI.2022.3223692.
• S. M. Abbas,  Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine and Warren J. Gross "High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, doi: 10.1109/TVLSI.2022.3153605.
• S. M. Abbas,  Marwan Jalaleddine and Warren J. Gross, "Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO)", Journal of Signal Processing Systems, 2022, doi:10.1007/s11265-022-01775-2.
• S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1098-1111, March 2017.
• Z. Qian, S. M. Abbas and C. Y. Tsui, "FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1854-1867, Sept. 2015.
•  S. M. Abbas, S. Lee, S. Baeg, S. Park, "An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory" IEEE Transactions on Computers, vol.PP, no.99, pp.1,1, doi: 10.1109/TC.2013.90.

Conference Papers

• S. M. Abbas, Marwan Jalaleddine, Chi-Ying Tsui and Warren J. Gross " Step-GRAND: A Low Latency Universal Soft-input Decoder", 2023 IEEE Globecom Workshops (GC Wkshps), Kuala Lumpur, Malaysia. Available Online: arXiv:2307.07133.
• S. M. Abbas, Marwan Jalaleddine and Warren J. Gross "GRAND for Rayleigh Fading Channels", 2022 IEEE GLOBECOM Workshops (GC Wkshps), 4–8 December 2022.
• S. M. Abbas, M. Jalaleddine and W. J. Gross, "High-Throughput VLSI Architecture for GRAND Markov Order," 2021 IEEE Workshop on Signal Processing Systems (SiPS), 2021, pp. 158-163, doi: 10.1109/SiPS52927.2021.00036.
• J. Li, S. M. Abbas, T. Tonnellier and W. J. Gross, "Reduced Complexity RPA Decoder for Reed-Muller Codes," 2021 11th International Symposium on Topics in Coding (ISTC), 2021, pp. 1-5, doi: 10.1109/ISTC49272.2021.9594060.
• S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine and Warren J. Gross "High-Throughput VLSI Architecture for soft decision decoding with ORBGRAND", 2021 IEEE International Conference on Acoustics, Speech and Signal Processing, 6-11 June 2021, Toronto,  Canada.
• S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross "High-Throughput VLSI Architecture for GRAND," 2020 IEEE Workshop on Signal Processing Systems (SiPS), Coimbra, Portugal, 2020, pp. 1-6, doi: 10.1109/SiPS50750.2020.9195254.
• S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “Concatenated LDPC-Polar Codes Decoding Through Belief Propagation” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4. 
• S. M. Abbas and Chi-Ying Tsui, "Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO" 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, 2016, pp. 1-5.
• S. M. Abbas, YouZhe Fan, Ji Chen and Chi-Ying Tsui, "Low complexity belief propagation polar code decoder" IEEE Workshop on Signal Processing Systems (SiPS), 2015, Hangzhou, pp. 1-6.
• S. M. Abbas, S. Hassan and Jongwon Yun, "Augmented reality based teaching pendant for industrial robot" International Conference on Control, Automation and Systems (ICCAS), 2012,  pp. 2210-2213.
• S. M. Abbas, Sanghyeon Baeg, Sungju Park “Multiple Cell Upsets tolerant Content Addressable Memory” International Reliability Physics Symposium (IRPS) April 2011, CA USA.

Patents

• VLSI architecture for implementing Guessing Random Additive Noise Decoding (GRAND) using Compute-in-Memory (CIM), S. M. Abbas and Chi-Ying Tsui, Patent Pending, 2023.
• Architecture for Guessing Random Additive Noise Decoding (GRAND), Warren J Gross, S. M. Abbas, Thibaud Tonnellier, US Patent Application No. 17330960, Dated: 2nd December, 2021
• Parallel LDPC decoder, H Lam, S. M. Abbas, Z Yang, Z Zhang, M Kwan, C Leung, K Tsang, US Patent App. 16/264,161, Dated: 8th June 2020 
• Method and apparatus for tolerating multi-cell upsets on content addressable memory, S. M. Abbas, S. Baeg, Patent Granted, Registration No. 1020100120903, Dated: 12th December, 2012.