TIE-12206 Post-Graduate Seminar on Pervasive Computing, 1-8 cr

Implementation TIE-12206 2019-16

Description

Verification with UVM (5cr)

Lessons

Assessment scale

Numerical evaluation scale (0-5)

Requirements

Completed exercises and a short presentation on a single UVM concept.
Voluntary assignments and electronic exam allow higher grades.

Additional information of course implementation

A seminar on SoC verification with SystemVerilog and UVM for master's and post-graduate students.

SystemVerilog and UVM are the current standards for SoC verification. On this course, you will learn the basics of UVM Environment and Test design with the object-oriented properties of SystemVerilog language on the side.

To attend this seminar course, you should already be familiar with Digital Design flow and VHDL language. Some experience of object-oriented programming is recommended.
Prerequisites:
TIE-5010X Digitaalisuunnittelu/Digital Design
TIE-50206 Logic Synthesis

If you attended TIE-11206 Verification with UVM (3cr) intensive course in November 2019, please contact the lecturer.

Sign up period extended until 12.1. If the maximum number of participants is exceeded, students are selected in the sign up order.