TIE-50206 Logic Synthesis, 5 cr

Additional information

Note to Finnish students: Kurssin kaikki materiaali on englanniksi, mutta harjoituksissa, tentissä ja muussa kommunikaatiossa voi vastata myös suomeksi riippuen henkilökunnan kielitaidosta. Luennoista voidaan harkinnan varaisesti ja erikseen pyydettäessä järjestää suomenkielisiä tiivistettyjä esityksiä.

Person responsible

Arto Perttula

Lessons

Implementation 1: TIE-50206 2015-01

Study type P1 P2 P3 P4 Summer

Lectures
Excercises

4 h/week
4 h/week
+2 h/week
+4 h/week

Lecture times and places: Monday 12 - 14 TC133 , Tuesday 10 - 12 TC133

Requirements

Passed exam and accepted exercise work.

Learning Outcomes

After this course, a student can implement a working digital system according to specification, i.e. convert a natural language specification into hardware description, verify it, and synthesize into FPGA chip. Moreover, students learn the relation between VHDL description and logic realization, can determine its behavior with given stimulus, and understand clock synhronization principles.

Content

Content Core content Complementary knowledge Specialist knowledge

1. Main phases in implementing a digital circuit. System realization in FPGA. Introduction to system design.

2. Basics of VHDL language and how it is synthesized into circuit.

3. Component verification and reuse. Principles of HDL simulator.

4. Systems with multiple clock signals. Synchronization interfaces.

Instructions for students on how to achieve the learning outcomes

Välikokeiden tai tentin arvosana sekä harjoitukset, joilla voi korottaa kurssin arvosanaa.

Assessment scale:

Numerical evaluation scale (1-5) will be used on the course

Study material

Type Name Author ISBN URL Additional information Examination material

Book RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Pong P. Chu 978-0471720928 Wiley-IEEE Press (April 14, 2006) Yes

Lecture slides Logic synthesis slides Erno Salminen Yes

Prerequisites

Course Mandatory/Advisable Description

TIE-50100 Digitaalisuunnittelu Mandatory

Additional information about prerequisites
Basic knowledge of digital logic is required, e.g. AND, OR, DFF, state machines, Karnaugh map...

Correspondence of content

Course Corresponds course Description

TIE-50206 Logic Synthesis, 5 cr TIE-50200 Logic Synthesis, 5 cr

Last modified 04.06.2015

Study type	P1	P2	P3	P4	Summer
Lectures Excercises		4 h/week 4 h/week	+2 h/week +4 h/week

Content	Core content	Complementary knowledge	Specialist knowledge
1.	Main phases in implementing a digital circuit.	System realization in FPGA. Introduction to system design.
2.	Basics of VHDL language and how it is synthesized into circuit.
3.	Component verification and reuse. Principles of HDL simulator.
4.	Systems with multiple clock signals. Synchronization interfaces.

Type	Name	Author	ISBN	URL	Additional information	Examination material
Book	RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability	Pong P. Chu	978-0471720928		Wiley-IEEE Press (April 14, 2006)	Yes
Lecture slides	Logic synthesis slides	Erno Salminen				Yes

Course	Mandatory/Advisable	Description
TIE-50100 Digitaalisuunnittelu	Mandatory

Course	Corresponds course	Description
TIE-50206 Logic Synthesis, 5 cr	TIE-50200 Logic Synthesis, 5 cr