Citing OpenASIP

In case you use OpenASIP in your research, please cite the following OpenASIP paper:

• Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala, Heikki Berg:
  "HW/SW Co-design Toolset for Customization of Exposed Datapath Processors",
  in Computing Platforms for Software-Defined Radio (book chapter pp 147-164), 2017 (download, BibTex).

Journal Articles and Conference/Workshop Papers

2024

• Topi Leppänen, Leevi Leppänen, Joonas Multanen, Pekka Jääskeläinen:
  Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL,
  IEEE Transactions on Very Large Scale Integration (VLSI), Early Access, Sep. 204 (download).
• Barry de Bruin, Kanishkan Vadivel, Mark Wijtvliet, Pekka Jääskeläinen, Henk Corporaal:
  R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA,
  ACM Transactions on Reconfigurable Technology and Systems, volume 17, issue 2, June 2024 (download).
• Jakub Zadnik, Anthony Trioux, Michel Kieffer, Markku Mäkitalo, Francois-Xavier Coudoux, Patrick Corlay, Pekka Jääskeläinen:
  Performance of Linear Coding and Transmission in Low-Latency Computer Vision Offloading,
  accepted to IEEE Wireless Communications and Networking Conference (WCNC) 2024
• Topi Leppänen, Joonas Multanen, Pekka Jääskeläinen:
  Towards Efficient OpenCL Pipe Specification for Hardware Accelerators,
  in the 12th International Workshop on openCL and SYCL (IWOCL), Apr. 2024 (download).

2023

• Kari Hepola, Joonas Multanen, Pekka Jääskeläinen:
  Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode,
  in IEEE Transactions on Computers (TC), Volume 73, issue 2, Feb. 2023 (download).
• Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen:
  AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management,
  in IEEE Nordic Circuits and Systems Conference (NorCAS 2023) (download).
• Niklas Rother, Leonard Mätzner, Pekka Jääskeläinen, Topi Leppänen, Jens Karsten Schleusner, Holger Christoph Blume:
  Synthetic Aperture Radar Algorithms on Transport Triggered Architecture Processors using OpenCL,
  in International Radar Conference 2023
• Maarten Molendijk, Floran de Putter, Manil Dev Gomony, Pekka Jääskeläinen and Henk Corporaal:
  BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC,
  in IEEE International Conference on Computer Design (ICCD 2023)
• Panagiotis Mousouliotis, Topi Leppanen, Pekka Jaaskelainen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos Antonopoulos, Nikolaos Voros:
  On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs,
  in the 19th International Symposium on Applied Reconfigurable Computing (ARC 2023)
• Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen:
  "Efficient OpenCL system integration of non-blocking FPGA accelerators",
  in Microprocessors and Microsystems (MICPRO), Vol. 97, Mar. 2023 (download).
• Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen:
  "AEX: Automated High-Level Synthesis of Compiler Programmable Co-processors",
  in Journal of Signal Processing Systems (JSPS), Feb. 2023​ (download).

2022

• Kanishkan Vadivel, Barry de Bruin, Pekka Jääskeläinen, Roel Jordans and Henk Corporaal:
  "Prebypass: Software Register File Bypassing for Reduced Interconnection Architecture",
  in Euromicro Conference on Digital Systems Design (DSD 2022) (download).
• Jakub Žádník, Markku Mäkitalo, Pekka Jääskeläinen:
  "Pruned Lightweight Encoders for Computer Vision",
  IEEE 24th International Workshop on Multimedia Signal Processing (MMSP 2022) download poster
• Topi Leppänen, Atro Lotvonen, Pekka Jääskeläinen:
  "Cross-vendor programming abstraction for diverse heterogeneous platforms",
  in Frontiers in Computer Science, Vol. 4, Oct. 2022 (download).
• Kari Hepola, Joonas Multanen and Pekka Jääskeläinen:
  "Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism",
  in 35th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2022) (download).
• Kari Hepola, Joonas Multanen and Pekka Jääskeläinen:
  "OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors",
  in 33rd IEEE International Conference on Applicationspecific Systems, Architectures and Processors (ASAP 2022) (download).
• Jakub Zadnik, Markku Mäkitalo, Jarno Vanne, Pekka Jääskeläinen:
  "Image and Video Coding Techniques for Ultra-Low-Latency",
  in ACM Computing Surveys (Volume 54, Issue 11s, January 2022) (download).

2021

• Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen:
  "Unified OpenCL Integration Methodology for FPGA Designs",
  in NorCAS 2021: IEEE Nordic Circuits and Systems Conference (download).
• Joonas Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jääskeläinen:
  "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory",
  in IEEE Transactions on Computers (Volume 71, Issue 9, September 2022) (download).
• Jan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen:
  "PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime",
  in SAMOS XXI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (virtual, July 2021) (download).
• Jakub Zadnik, Markku Mäkitalo, Jussi Iho, Pekka Jääskeläinen:
  "Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks",
  in EUVIP 2021: 9th European Workshop on Visual Information Processing (virtual, 23-25 June 2021) (download).
• Joost Hoozemans, Kati Tervo, Pekka Jääskeläinen, Zaid Al-Ars:
  "Energy Efficient Multistandard Decompressor ASIP",
  in ICCDE 2021: 7th International Conference on Computing and Data Engineering (virtual, January 2021) (download).

2020

• Joonas Multanen, Kari Hepola, Pekka Jääskeläinen:
  "Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency",
  in ICCD 2020: The 38th IEEE International Conference on Computer Design (virtual, October, 2020) (download).
• Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen:
  "TTA-SIMD Soft Core Processors",
  in FPL2020: 30th International Conference on Field-Programmable Logic and Applications (virtual, August-September, 2020) (download).
• Joonas Multanen, Heikki Kultala, Kati Tervo, Pekka Jääskeläinen:
  "Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications",
  in Journal of Signal Processing Systems (2020) (download).

2019

• Kanishkan Vadivel, Pekka Jääskeläinen, Roel Jordans, Heikki Kultala, Sander Stuijk, Henk Corporaal:
  "Towards Efficient Code Generation for Exposed Datapath Architectures",
  in SCOPES 2019: 22nd International Workshop on Software and Compilers for Embedded Systems (Sankt Goar, Germany, May, 2019) (download).
• Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Holger Blume, Guillermo Payá Vayá, Pekka Jääskeläinen:
  "Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments",
  in SAMOS XIX: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2019) (download).
• Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jeronimo Gastrillon:
  "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory",
  in ACM/IEEE International Symposium on Low Power Electronics and Design (Lausanne, Switzerland, July 2019) (download).
• Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen:
  "AEx: Automated Customization of Exposed Datapath Soft-Cores",
  in Euromicro Conference on Digital System Design (Kallithea, Greece, August 2019) (download).
• Jakub Zadnik, Jarmo Takala:
  "Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture",
  in 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
• Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala:
  "LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor",
  in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Volume 27, Issue 5, May 2019) (download).

2018

• Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen, Timo Viitanen, Aleksi Tervo, Jarmo Takala:
  "LoTTA: Energy-Efficient Processor for Always-On Applications",
  in SiPS 2018: IEEE Workshop on Signal Processing Systems (Cape Town, South Africa, October 2018) (download).
• Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen:
  "Energy-Delay Trade-Offs in Instruction Register File Design",
  in IEEE Nordic Circuits and Systems Conference (Tallinn, Estonia, October 2018) (download).
• Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jego and Yvon Savaria:
  "Transport Triggered Polar Decoders",
  in The 10th International Symposium on Turbo Codes & Iterative Information Processing (Hong Kong, China, December 2018) (download).
• Pekka Jääskeläinen, Ville Korhonen, Matias Koskela, Jarmo Takala, Karen Egiazarian, Aram Danielyan, Cristóvão Cruz, James Price, Simon Mcintosh-Smith:
  "Exploiting Task Parallelism with OpenCL: A Case Study",
  in Journal of Signal Processing Systems, vol. 91, issue 1, October 2018 (download).
• Jos IJzerman, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Lasse Lehtonen, Maurice Peemen, Henk Corporaal, Jarmo Takala:
  "AivoTTA: An Energy Efficient Programmable Accelerator for CNN-Based Object Recognition",
  in SAMOS XVIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2018) (download).
• Pekka Jääskeläinen, John Glossner, Martin Jambor, Aleksi Tervo, Matti Rintala:
  "Offloading C++17 Parallel STL on System Shared Virtual Memory Platforms",
  in 3rd Workshop on Open Source Supercomputing (OpenSuco3 within ISC 2018, June, Frankfurt, Germany) (download).
• Pekka Jääskeläinen, Aleksi Tervo, Guillermo Paya-Vaya, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume. (2018).:
  "Transport-Triggered Soft Cores",
  in 2018 IEEE International Parallel and Distributed Processing Symposium, Workshops (IPDPSW) (download).
• Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen. Jarmo Takala.:
  "Instruction Fetch Energy Reduction with Biased SRAMs",
  in Journal of Signal Processing Systems, 2018 (download).
• Timo Viitanen, Janne Helkala, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg:
  "Variable Length Instruction Compression on Transport Triggered Architectures",
  in International Journal of Parallel Programming, 2018 (download).

2017

• Aghababaeetafreshi, M., Korpi, D., Koskela, M., Jääskeläinen, P., Valkama, M. & Takala, J.:
  "Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors",
  in Journal of Signal Processing Systems 2017 (download).
• Heikki Kultala, Pekka Jääskeläinen, Johannes Ijzerman, Timo Viitanen, Markku Mäkitalo, Jarmo Takala:
  "Exposed Datapath Optimizations for Loop Scheduling",
  in SAMOS XVII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2017) (download).
• Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala, Heikki Berg:
  "HW/SW Co-design Toolset for Customization of Exposed Datapath Processors",
  in Computing Platforms for Software-Defined Radio (book chapter pp. 147-164), 2017 (download).

2016

• Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala, Jarmo Takala:
  "Improving Code Density with Variable Length Encoding Aware Instruction Scheduling",
  in Journal of Signal Processing Systems, September 2016, vol. 84, issue 3 (download).
• Tomi Äijö, Pekka Jääskeläinen, Tapio Elomaa, Jarmo Takala:
  "Integer Linear Programming-Based Scheduling for Transport Triggered Architectures",
  in ACM Transactions on Architecture and Code Optimization, January 2016, vol. 12, issue 4 (download).
• Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
  "Xor-Masking: a Low-Overhead Method for Instruction Fetch Energy Reduction with Emerging SRAM Technologies",
  in SiPS 2016: IEEE Workshop on Signal Processing Systems (Dallas, Texas, October 2016) (download).
• Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Karen Egiazarian, Aram Danielyan, Cristóvão Cruz:
  "OpenCL Programmable Exposed Datapath High Performance Low-Power Computational Imaging Accelerator",
  in IEEE Nordic Circuits and Systems Conference (Copenhagen, Denmark, November 2016) (download).
• Mona Aghababaeetafreshi, Matias Koskela, Dani Korpi, Pekka Jääskeläinen, Mikko Valkama, Jarmo Takala:
  "Software Defined Radio Implementation of Adaptive Nonlinear Digital Self-interference Cancellation for Mobile Inband Full-Duplex Audio",
  in GlobalSIP: 4th IEEE Global Conference on Signal & Information Processing (Washington D.C., USA, December 2016).
• Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
  "Aggressively Bypassing List Scheduler for Transport Triggered architectures",
  in SAMOS XVI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2016) (download).
• N.Behmann, C. Seifert, G. Paya-Vaya, H. Blume, P. Jääskeläinen, J.Multanen, H. Kultala, J. Takala, J. Thiemann, S. van de Par:
  "Customized High Performance Low Power Processor for Binaural Speaker Localization",
  in IEEE Int'l Conference on Electronics, Circuits, & Systems (Monte Carlo, Monaco, December 2016) (download).

2015

• Jääskeläinen Pekka, Kultala Heikki, Viitanen Timo, Takala Jarmo:
  "Code Density and Energy Efficiency of Exposed Datapath Architectures",
  in Journal of Signal Processing Systems, vol. 80, issue 1, July 2015 (download).
• Heikki Kultala, Joonas Multanen, Pekka Jääskeläinen, Timo Viitanen, and Jarmo Takala:
  "Impact of Operand Sharing to the Processor Energy Efficiency",
  in CADS: 18Th CSI International Symposium on Computer Architecture & Digital Systems (Tehran, Iran, October 2015) (download).
• Ville Korhonen , Pekka Jääskeläinen, Matias Koskela, Jarmo Takala:
  "Rapid Customization of Image Processors Using Halide",
  in GlobalSIP: 3rd IEEE Global Conference on Signal & Information Processing (Orlando, Florida, December 2015) (download).
• Joonas Multanen, Timo Viitanen, Henry Linjamäki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila and Tommi Zetterman:
  "Power Optimizations for a Transport Triggered SIMD Processor",
  in SAMOS XV: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2015) (download).

2014

• Kultala Heikki, Viitanen Timo, Jääskeläinen Pekka, Helkala Janne, Takala Jarmo:
  "Compiler Optimizations for Code Density of Variable Length Instructions",
  in 2014 IEEE Workshop on Signal Processing Systems (SiPS) (download).
• Viitanen Timo, Kultala Heikki, Jääskeläinen Pekka, Takala Jarmo:
  "Heuristics for Greedy Transport Triggered Architecture Interconnect Exploration",
  in International Conference on Compilers, Architecture and Synthesis for Embedded Systems 2014 (CASES 14) (download).
• Helkala Janne, Viitanen Timo, Kultala Heikki, Jääskeläinen Pekka, Takala Jarmo, Zetterman Tommi, Berg Heikki:
  "Variable Length Instruction Compression on Transport Triggered Architectures",
  in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014 (download).

2013

• Tomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
  "Low-Power Application-Specific FFT Processor for LTE Applications",
  in SAMOS XIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2013). (doi)
• Heikki Kultala, Otto Esko, XianJun Jiao, Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Tommi Zetterman, Heikki Berg:
  "Turbo Decoding on Tailored OpenCL Processor",
  in IWCMC 2013: International Wireless Communications & Mobile Computing Conference (Cagliari, Italy, July 2013). (doi)
• Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala,
  "Inexpensive Correctly Rounded Floating-Point Division and Square Root With Input Scaling"
  in Proc. of IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, Oct 16-18, 2013 (pdf available)
• Timo Viitanen, Pekka Jääskeläinen, Otto Esko, Jarmo Takala,
  "Simplified Floating Point Division and Square Root"
  in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing 2013, Vancouver, Canada, May 26-31, 2013 (pdf available)

2011

• Pekka O. Jääskeläinen, Erno O. Salminen, Carlos S. de La Lama, Jarmo H. Takala, and Jose Ignacio Martinez,
  "TCEMC: A Co-Design Flow for Application-Specific Multicores",
  in Proc. of IC-SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 18-21, Samos, Greece (download)
• Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala,
  "Customizable Datapath Integrated Lock Unit,"
  in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011 (pdf available)
• Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala
  "Operation Set Customization in Retargetable Compilers",
  Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 6-9 Nov 2011, Pacific Grove, California (pdf available)
• Vladimír Guzma, Teemu Pitkänen, Jarmo Takala,
  "Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption,"
  in Proc. of International Symposium on System on Chip 2011, Tampere, Finland, October 31-November 2, 2011
• Vladimír Guzma, Teemu Pitkänen, and Jarmo H. Takala,
  "Instruction Buffer with Limited Control Flow and Loop Nest Support,"
  in Proc. of IC-SAMOS 2011: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 18-21, Samos, Greece.
• Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Jarmo Takala:
  "Design methodology for accelerating software executions with FPGA",
  in SiPS 2010 IEEE Workshop on Signal Processing Systems, San Francisco, USA, October 2010 Link to the publisher's page.
• Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, Jose Ignacio Martinez,
  “Customized Exposed Datapath Soft-Core Design Flow with Compiler Support”,
  in 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, August-September 2010, (PDF available)
• Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, and Jarmo Takala,
  OpenCL-based Design Methodology for Application-Specific Processors,
  in Transactions on HiPEAC: Volume 5, Issue 4, 2011
• Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
  "Design Methodology for Offloading Software Executions to FPGA",
  in Journal of Signal Processing Systems, November 2011, vol. 65, issue 2. (doi)

2010

• Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala,
  “OpenCL-based Design Methodology for Application-Specific Processors”,
  in SAMOS X: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July 2010 (PDF available)

2009

• L. Nurmi, P. Salmela, P. Kellomäki, P. Jääskeläinen, J. Takala
  "Reconfigurable Video Decoder with Transform Acceleration".
  in Proc. of the 2009 IEEE Workshop on Signal Processing Systems, SIPS 2009, October 7-9, Tampere, Finland. Link to the publisher's page.
• V. Guzma, T. Pitkänen, P. Kellomäki, J. Takala,
  "Reducing Processor Energy Consumption by Compiler Optimization", in Proc. of the 2009 IEEE Workshop on Signal Processing Systems, SIPS 2009, October 7-9, Tampere, Finland.
• Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala,
  "Programmable and Scalable Architecture for Graphics Processing Units", Workshop of SAMOS IX:
  Embedded Computer Systems: Architectures, Modeling, and Simulation (Samos, Greece, July 2009). (PDF available)
• Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, and Jarmo Takala,
  Programmable and Scalable Architecture for Graphics Processing Units,
  Transactions on HiPEAC: Volume 5, Issue 3

2008

• Guzma, V.; Bhattacharyya, S.S.; Kellomaki, P.; Takala, J.,
  "Trade-offs in mapping high-level dataflow graphs onto ASIPs,"
  System-on-Chip, 2008. SOC 2008. International Symposium on , vol., no., pp.1-4, 5-6 Nov. 2008 URL: link to publishers page
  
• Guzma, V.; Bhattacharyya, S.S.; Kellomaki, P.; Takala, J.,
  ""An integrated ASIP design flow for digital signal processing applications,"
  Applied Sciences on Biomedical and Communication Technologies, 2008. ISABEL '08. First International Symposium on , vol., no., pp.1-5, 25-28 Oct. 2008 URL: link to publishers page
  
• Pertti Kellomäki, Vladimir Guzma, Jarmo Takala,
  “"Safe Pre-Pass Software Bypassing for Transport Triggered Processors” ,
  Acta Technica Napocensis, vol. 49, no. 3, 2008 - special issue, pp.5-10 link to publishers page
• Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö,
  ""Reducing Context Switch Overhead with Compiler-Assisted Threading",
  in The 3rd International Workshop on Embedded Software Optimization, Shanghai, China, Dec, 2008 (PDF available)
• V. Guzma, P. Jääskeläinen, P. Kellomäki, and J. Takala,
  “Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic,”
  in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 8th Int. Workshop SAMOS VIII.,
  M. Bereković, N. Dimopoulos, and S. Wong, Eds., Volume 5114, pp. 23–32. Springer-Verlag, Berlin, Germany, 2008 (PDF available)
• Pekka Jääskeläinen, Heikki Kultala, Teemu Pitkänen, and Jarmo Takala,
  “Reducing the Overheads of Hardware Acceleration Through Datapath Integration”
  in Electronic Imaging 2008 (San Jose, USA, January 2008) (pdf available)

2007

• Pekka Jääskeläinen, Vladimír Guzma, Viljami Korhonen,
  “Resource Conflict Detection in Simulation of Function Unit Pipelines” (extended version), in JSA Special Issue on SAMOS 2007, Elsevier. (pdf available)
• P. Jääskeläinen, V. Guzma, and J. Takala,
  "Resource Conflict Detection in Simulation of Function Unit Pipelines" ,
  in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
  S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page.
• J.K. Tanskanen, T. Pitkänen, R. Mäkinen, and Jarmo Takala,
  "Parallel Memory Architecture for TTA Processor" ,
  in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
  S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page.
• T. Pitkänen, T. Partanen, and Jarmo Takala,
  "Low-Power Twiddle Factor Unit for FFT Computation" ,
  in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS VII.,
  S. Vassiliadis, M. Bereković, T.D. Hämäläinen, Volume LNCS 4599, pp. 233–240. Springer-Verlag, Berlin, Germany, 2007 (pdf) Link to the publisher's page.

2006

• T. Pitkänen, R. Mäkinen, J. Heikkinen, T. Partanen, and J. Takala,
  "Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform",
  in Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 6th Int. Workshop SAMOS VI,
  S. Vassiliadis, S. Wong, T.D. Hämäläinen, Volume LNCS 4017, pp. 227–236. Springer-Verlag, Berlin, Germany, 2006 (pdf)
• P. Salmela, P. Jääskeläinen, T. Järvinen, and J. Takala,
  "Software pipelining support for transport triggered architecture processors",
  in Embedded Computer Systems: Architectures, Modeling, and Simulation Proc. 6th Int. Workshop SAMOS VI, Lecture Notes in Computer Science
• T. Pitkänen, R. Mäkinen, J. Heikkinen, T.Partanen, J. Takala,
  "Transport triggered architecture processor for mixed-radix FFT",
  in Proc. Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA (2006) (pdf)
• P. Salmela, R. Mäkinen, P. Jääskeläinen, and J. Takala,
  "Loop scheduling for transport triggered architecture processors",
  in International Symposium on System-on-Chip (SoC), Tampere, Finland, Nov. 13-16, 2006, pp. 45-48.

2005

• J. Heikkinen, J. Takala, and H. Corporaal,
  "Dictionary-Based Program Compression on TTAs: Effects on Area and Power Consumption",
  in Proc. IEEE Workshop on Signal Processing Systems, Athens, Greece, Nov. 2-4, 2005, pp. 479-484. (pdf)
• T. Pitkänen, T. Rantanen, A. Cilio, and J. Takala,
  "Hardware Cost Estimation for Application-Specific Processor Design",
  in Embedded Comput. Syst.: Architectures Modeling Simulation, Proc. 5th Int. Workshop SAMOS V,
  T. D. Hämäläinen, A. D. Pimentel, J. Takala, and S. Vassiliadis, Eds. Lecture Notes in Computer Science,
  vol. LNCS 3553, pp. 212-221. Springer-Verlag, Berlin, Germany, 2005. (pdf)
• P. Salmela, T. Järvinen, T. Sipilä, and J. Takala,
  "256-state rate 1/2 Viterbi decoder on TTA processor",
  in proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Samos, Greece, 23-25 Jul. 2005, pp. 370-375.
• P. Salmela, T. Järvinen, T. Sipilä, and J. Takala,
  "Scalable FIR filtering on transport triggered architecture processor",
  in proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS 2005), Iasi, Romania, 14-15 Jul. 2005, pp. 493-496.
• J. Heikkinen, A. Cilio, J. Takala, and H. Corporaal,
  "Dictionary-Based Program Compression on Transport Triggered Architectures",
  in Proc. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, May 23-26, 2005, pp. 1122-1125. (pdf)

2004

• J. Heikkinen, P. Kuukkanen, and J. Takala,
  "Bitwise and Dictionary Modeling for Code Compression on Transport Triggered Architectures",
  in WSEAS Trans. on Circuits and Systems, vol. 3, iss. 9, pp. 1750-1755, Nov. 2004. (pdf)

2003

• R. Mäkelä, J. Takala, and O. Vainio,
  "Analysis of Different bus Architectures for Transport Triggered Architectures",
  in Proc. 21st Norchip Conf., Riga, Latvia, Nov. 10-11, 2003, pp. 56-59. (pdf)
• J. Heikkinen, T. Rantanen, A. Cilio, J. Takala, and H. Corporaal,
  "Immediate Optimization for Compressed Transport Triggered Architecture Instructions",
  in Proc. Int. Symp. on System-on-Chip, Tampere, Finland, Nov. 19-21 2003, pp. 65-68. (pdf)
• J. Heikkinen, T. Rantanen, A. Cilio, J. Takala, and H. Corporaal,
  "Evaluating Template-Based Instruction Compression on Transport Triggered Architectures",
  in Proc. Int. Workshop on System-on-Chip for Real-Time Applications, Calgary, Canada, June 30 - July 2 2003, pp. 192-195. (pdf)

2002

• J. Heikkinen, J. Sertamo, T. Rautiainen and J. Takala,
  "Design of Transport Triggered Architecture Processor for Discrete Cosine Transform",
  in Proc. 15th Ann. IEEE Int. ASIC/SOC Conf., Rochester, NY, U.S.A., Sept. 25-28 2002, pp. 87-91. (pdf)
• J. Heikkinen, J. Takala and J. Sertamo,
  "Code Compression on Transport Triggered Architectures",
  in Proc. Int. Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 6-7 2002, pp. 186-195. (pdf)
• J. Heikkinen, J. Takala, A. Cilio and H. Corporaal,
  "On Efficiency of Transport Triggered Architectures",
  in Advances in Systems Engineering, Signal Processing and Communications, N. Mastorakis, Ed.,
  pp. 25-29. WSEAS Press, New York, NY, U.S.A., 2002. (pdf)

Doctoral Dissertations

• Joonas Multanen:
  Energy-Efficient Instruction Streams for Embedded Processors (November, 2021) (download)
• Pekka Jääskeläinen:
  From Parallel Programs to Customized Parallel Processors (September, 2012) (download)
• Perttu Salmela:
  Implementations of Baseband Functions for Digital Receivers (August, 2009) (link)
• Jari Heikkinen:
  Program Compression in Long Instruction Word Application-Specific Instruction-Set Processors (December, 2007) (pdf)

Master's Theses

• Robin Bijl:
  Adding fault tolerance to OpenCL (2023) (link)
• Jyry Uitto:
  Offloading computation with a minimized OpenCL runtime from a nano drone (2023) (link)
• Kari Hepola:
  Generation of Customized RISC-V Implementations (2022) (link)
• Topi Leppänen:
  Scalability optimizations for multicore soft processors (2021) (link)
• Jan Solanti:
  Distributed Low Latency Computing With OpenCL: A Scalable Multi-Access Edge Computing Framework (2020) (link)
• Aleksi Tervo:
  Optimizing Transport-Triggered Architectures for Field-Programmable Gate Arrays (2018) (link)
• Henry Linjamäki:
  Instruction Memory Hierarchy Generation for Customized Processors (2015) (link)
• Ville Korhonen:
  Portable OpenCL Out-of-Order Execution Framework for Heterogeneous Platforms (December, 2014) (link)
• Janne Helkala:
  Variable Length Instruction Compression on Transport Triggered Architectures (June, 2014) (link)
• Mikko Järvelä:
  Vector Operation Support for Transport Triggered Architectures (June, 2014) (link)
• Timo Viitanen:
  Floating-Point Arithmetic in Transport Triggered Architectures (December, 2012) (link)
• Otto Esko:
  ASIP Integration and Verification Flow (June, 2011) (link)
• Veli-Pekka Jääskeläinen:
  Retargetable Compiler Backend for Transport Triggered Architectures (Feb, 2010) (pdf)
• Jari Mäntyneva:
  Automated Design Space Exploration of Transport Triggered Architectures (July, 2009) (pdf)
• Viljami Korhonen:
  Tools for Fast Design of Application-Specific Processors (January, 2009) (pdf)
• Ari Metsähalme:
  Instruction Scheduler Framework for Transport Triggered Architectures (April, 2008) (pdf)
• Lasse Laasonen:
  Program Image and Processor Generator for Transport Triggered Architectures (April, 2007) (pdf)
• Mikael Lepistö:
  Assembly Compiler for Parametrizable Parallel Processor (June, 2006) (pdf)
• Pekka Jääskeläinen:
  Instruction Set Simulator for Transport Triggered Architectures (September, 2005) (pdf)
• Risto Mäkinen:
  Fast Fourier Transform on Transport Triggered Architectures (October, 2005) (pdf)
• Teemu Pitkänen:
  Experiments of TTA on ASIC Technology (August, 2005) (pdf)
• Jari Heikkinen:
  DSP Applications on Transport Triggered Architectures (May, 2001) (pdf)

Bachelor's Theses

• Aleksi Tervo:
  Programmable Inter-Device Block Transfer Hardware for Customized Heterogeneous Computing Platforms (June, 2017) (pdf)
• Otto Esko:
  Siirtoliipaistujen prosessorien käyttäminen FPGA-pohjaisissa järjestelmäpiireissä (Utilizing Transport-Triggered Processors on FPGA-based System-on-Chip) (March, 2011) (pdf)

Technical Reports

• Miika Niiranen: Transport Triggered Architectures on FPGA (October, 2004) (pdf)

Publications using OpenASIP/TTA from outside the CPC group

Unlike the above listed publications, the publications listed below are such where we consider CPC group's contribution was either very minor or they were completely authored outside our group. Please let us know if we have missed any, we are happy to list them here!

• Kavitha Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee:
  "Transport Triggered near Memory Accelerator for Deep Learning",
  in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (download).
• Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jego, Yvon Savaria:
  "Transport Triggered Polar Decoders",
  in 2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC) (download).
• Jukka Teittinen, Markus Hiienkari, Indrė Žliobaitėb, Jaakko Hollmen, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen:
  "A 5.3 pJ/op approximate TTA VLIW tailored for machine learning",
  in Microelectronics Journal, Volume 61, March 2017 (download).
• Yviquel Hervé, Sanchez Alexandre, Jääskeläinen Pekka, Takala Jarmo, Raulet Mickaël, Casseau Emmanuel:
  "Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs",
  in Journal of Signal Processing Systems, vol. 80, issue 1, July 2015 (download).
• Janne Janhunen, Pekka Jääskeläinen, Jari Hannuksela, Tero Rintaluoma, Aki Kuusela:
  "Programmable In-loop Deblock Filter Processor for Video Decoders",
  in SiPS 2014: IEEE Workshop on Signal Processing Systems (Belfast, UK, October 2014) (download).
• Nyländen Teemu, Boutellier Jani, Nikunen Karri, Hannuksela Jari, Silvén Olli:
  "Low-power Reconfigurable Miniature Sensor Nodes for Condition Monitoring",
  in International Journal of Parallel Programming (download).
• Hautala Ilkka, Boutellier Jani, Hannuksela Jari, Silvén Olli:
  "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering",
  in IEEE Transactions on Circuits and Systems for Video Technology (download).
• Ghazi Amanullah, Boutellier Jani, Abdelaziz Mahmoud, Lu Xiaojia, Anttila Lauri, Cavallaro Joseph R, Bhattacharyya Shuvra S, Valkama Mikko, Juntti Markku:
  "Low Power Implementation of Digital Predistortion Filter on a Heterogeneous Application Specific Multiprocessor",
  in The 39th IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), Florence, Italy (download).
• Rister B., Jääskeläinen P., Silven O., Hannuksela J.:
  "Parallel Programming of a Symmetric Transport-Triggered Architecture with Applications in Flexible LDPC Encoding",
  in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
• Yviquel H., Sanchez A., Jääskeläinen P., Takala J.:
  "Efficient Software Synthesis of Dynamic Dataflow Programs",
  in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).
• Boutellier J, Raulet M, Silvén O:
  "Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs",
  in Journal of Signal Processing Systems, Springer, Volume 73, Issue 2, pp. 137-142.
• Yviquel H, Boutellier J, Raulet M, Casseau E:
  "Automated design of networks of Transport-Triggered Architecture processors using Dynamic Dataflow Programs",
  in Signal Processing: Image Communication (special issue on Reconfigurable Media Coding), Elsevier.
• Boutellier J, Ersfolk J, Ghazi A, Silvén O:
  "High-Performance Programs by Source-Level Merging of RVC-CAL Dataflow Actors",
  in IEEE Workshop on Signal Processing Systems (SiPS 2013), Taipei, Taiwan, Oct 16-18.
• Ghazi A, Boutellier J, Hannuksela J, Silvén O, Shahabuddin S:
  "Programmable Implementation of Zero-Crossing Demodulator on an Application Specific Processor",
  in IEEE Workshop on Signal Processing Systems (SiPS 2013), Taipei, Taiwan, Oct 16-18.
• Hautala I, Boutellier J, Hannuksela J:
  "Programmable Low Power Implementation of the HEVC Adaptive Loop Filter",
  in The 38th IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), Vancouver, Canada, May 26-31.
• Ghazi A, Boutellier J, Hannuksela J, Silvén O, Janhunen J:
  "Low-complexity SDR Implementation of IEEE 802.15.4 (ZigBee) Baseband Transceiver on Application Specific Processor",
  in Proc. Wireless Innovation Forum Conference on Wireless Communications Technologies and Software Defined Radio (SDR-WInnComm), Washington, DC, USA, Jan 8-10.
• Shahabuddin S, Janhunen J, Bayramoglu MF, Juntti M:
  "Design of a unified transport triggered processor for LDPC/turbo decoder",
  in International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), Samos, Greece.
• Hänninen T, Janhunen J, Juntti M:
  "Novel detector implementations for 3G LTE downlink and uplink",
  in Analog Integrated Circuits and Signal Processing.
• Shahabuddin S, Janhunen J, Juntti M:
  "Design of a transport triggered architecture processor for a flexible iterative turbo decoder",
  in Proceedings of Wireless Innovation Forum Conference on Wireless Communications Technologies and Software Radio (SDR Wincomm), Washington, D.C., USA, Jan. 2013.
• Shahabuddin S., Janhunen J, Juntti M, Ghazi A, Silvén O:
  "Design of a transport triggered vector processor for turbo Decoding",
  in Springer Journal of Analog Integrated Circuits and Signal Processing.
• Janhunen J, Pitkanen T, Silvén O, Juntti M:
  "Programmable implementations of MIMO-OFDM detectors: Design, benchmarking and comparison",
  in International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, 1581 - 1584.
• Nyländen T, Boutellier J, Nikunen K, Hannuksela J, Silvén O:
  "Reconfigurable Miniature Sensor Nodes for Condition Monitoring",
  in Proc. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), Samos, Greece, July 16-19.
• Boutellier J, Lundbom I, Janhunen J, Ylimäinen J, Hannuksela J:
  "Application-specific instruction processor for extracting local binary patterns",
  in Proc. Conference on Design and Architectures for Signal and Image Processing (DASIP 2012), Karlsruhe, Germany, Oct. 23-25.
• Boutellier J, Raulet M, Silvén O:
  "Automatic Synthesis of TTA Processor Networks from RVC-CAL Dataflow Programs",
  in Proc. IEEE Workshop on Signal Processing Systems (SiPS), Beirut, Lebanon, Oct. 4-7. 2011.
• Nyländen T, Janhunen J, Hannuksela J, Silvén O:
  "FPGA based application specific processing for sensor nodes.",
  in Proc. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI), Samos, Greece.
• Janhunen J, Pitkänen T, Silvén O, Juntti M.:
  "Fixed-and floating-point processor comparison for MIMO-OFDM detector",
  in International Conference on Acoustics, Speech and Signal Processing (2011), Prague, Czech Republic.
• Antikainen J, Salmela P, Silvén O, Juntti M, Takala J, Myllylä M:
  "Fine-grained Application-Specific Instruction Set Processor Design for the K-best List Sphere Detector Algorithm",
  in International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS XIII).
• J.Janhunen, J. Antikainen, O. Silvén, M. Juntti, M. Myllylä,:
  "Programmable Processor Comparison Based on the K-Best List Sphere Detector Algorithm",
  in International Symposium on Wireless Personal Multimedia Communications (WPMC), September 2008, Saariselkä, Finland (won the best student paper award).

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