Arto Oinonen
University Instructor, System-on-Chip Design
Tampere University
arto.oinonen [at] tuni.fi (arto[dot]oinonen[at]tuni[dot]fi)
phone number+358469228313
Latest publications
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud
Sjövall, P., Oinonen, A., Teuho, M., Vanne, J. & Hämäläinen, T. D., Oct 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEEResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Feasibility of FPGA accelerated IPsec on cloud
Vajaranta, M., Oinonen, A., Hämäläinen, T. D., Viitamäki, V., Markunmäki, J. & Kulmala, A., 1 Nov 2019, In: Microprocessors and Microsystems. 71, 102861.Research output: Contribution to journal › Article › Scientific › peer-review
Visualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud
Sjövall, P., Teuho, M., Oinonen, A., Vanne, J. & Hämäläinen, T., 2019, 2019 IEEE International Conference on Visual Communications and Image Processing (VCIP). IEEEResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Feasibility of FPGA accelerated IPsec on cloud
Vajaranta, M., Viitamäki, V., Oinonen, A., Hämäläinen, T. D., Kulmala, A. & Markunmäki, J., 31 Aug 2018, 2018 Euromicro Conference on Digital System Design (DSD). IEEEResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Kvazaar 4K HEVC Intra Encoder on FPGA Accelerated Airframe Server
Sjövall, P., Viitamäki, V., Oinonen, A., Vanne, J., Hämäläinen, T. D. & Kulmala, A., 2017, Proceedings of 2017 IEEE International Workshop on Signal Processing Systems. IEEE, p. 1-6Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review